/*
 * Copyright (c) 2006-2020, YICHIP Development Team
 * @file     g_psram.c
 * @brief    This file contains all the functions prototypes for the psram firmware library.
 *
 * Change Logs:
 * Date            Author             Version        Notes
 * 2021-05-19      dengzhiqian        V1.0.0         the first version  
 */
 
#ifndef __G_PSRAM_H__
#define __G_PSRAM_H__

#include "g_1903.h"
extern unsigned char FLAG_QUAD;

//#define DEBUG_PRINTF
#define PSRAM_BASEADDR   0xfb600

//psram internal reg
#define PSRAM_CTRL_REG					*(volatile unsigned int*)(PSRAM_BASEADDR + 0x00)
#define PSRAM_TASK_TABLE_ADDR_REG		*(volatile unsigned int*)(PSRAM_BASEADDR + 0x04)
#define PSRAM_TASK_TRIG_SRC_REG			*(volatile unsigned int*)(PSRAM_BASEADDR + 0x08)
#define PSRAM_IRQ_CTRL_REG				*(volatile unsigned int*)(PSRAM_BASEADDR + 0x0C)
	
#define PSRAM_Read_Cmd						0x03
#define PSRAM_Fast_Read_Cmd					0x0b
#define PSRAM_Fast_Read_Quad_Cmd			0xeb
#define PSRAM_Write_Cmd						0x02
#define PSRAM_Quad_Write_Cmd				0x38
#define PSRAM_Wrapped_Read_Cmd				0x8b
#define PSRAM_Wrapped_Write_Cmd				0x82
#define PSRAM_Mode_Register_Read_Cmd		0xb5
#define PSRAM_Mode_Register_Write_Cmd		0xb1
#define PSRAM_Enter_Quad_Mode_Cmd			0x35
#define PSRAM_Exit_Quad_Mode_Cmd			0xf5
#define PSRAM_Reset_Enable_Cmd				0x66
#define PSRAM_Reset_Cmd						0x99
#define PSRAM_Burst_Length_Toggle_Cmd		0xc0
#define PSRAM_Read_ID_Cmd					0x9f

#define SINGLE_LINE_DI_AND_DO_MODE		0x00
#define SINGLE_LINE_DIO_MODE			0x01
#define TRANSFER_DIR_READ_PSRAM			0x00
#define TRANSFER_DIR_WRITE_PSRAM		0x01
#define DATA_WIDTH_1_BIT				0x00
#define DATA_WIDTH_2_BIT				0x01
#define DATA_WIDTH_4_BIT				0x02
#define ADDR_WIDTH_1_BIT				0x00
#define ADDR_WIDTH_2_BIT				0x01
#define ADDR_WIDTH_4_BIT				0x02
#define CDM_AND_DATA					0x00
#define CDM_ONLY						0x01
#define CDM_WIDTH_1_BIT					0x00
#define CDM_WIDTH_2_BIT					0x01
#define CDM_WIDTH_4_BIT					0x02
#define DISABLE_CHAIN					0x00
#define ENABLE_CHAIN					0x01

#define PSRAM_DMA_ENABLE	0x01
#define PSRAM_DMA_DISABLE	0x00

#define SCK_HIGH_DIV	1
#define SCK_LOW_DIV		1

#define TASK0	0x01
#define TASK1	0x02
#define TASK2	0x04
#define TASK3	0x08
#define TASK4	0x10
#define TASK5	0x20
#define TASK6	0x40
#define TASK7	0x80

typedef struct
{
	unsigned int    TaskIndex;
	unsigned char   SckHiDiv;
	unsigned char   SckLoDiv;
	unsigned char   SingleLineIOMode;
	unsigned char   TransferDir;	
	unsigned char   DataPhaseWidth;
	unsigned char   WaitCycle;
	unsigned char   AddrPhaseWidth;
	unsigned char   CmdOnly;
	unsigned char   CmdPhaseWidth;
	unsigned char   QspiCmd;
	unsigned int    QspiAddr;
	unsigned int    QspiTransferLen;
	unsigned int   	DmaLen;
	unsigned int    DmaSaddr;
	unsigned char   DmaFixedAddr;
	unsigned int    ChainTaskAddr;
	unsigned char   ChainEnable;
} G_PSRAM_TaskTypeDef;


void G_PSRAM_DataRead(unsigned int addr,unsigned int len, unsigned char *rbuf);
void G_PSRAM_DataWrite(unsigned int addr,unsigned int len, unsigned char *wbuf);
void G_PSRAM_Enable_QUAD(void);
char G_GET_PSRAM_Status(void);

#endif	/* __G_PSRAM_H__ */

